The present invention relates to a method of forming a well of one conductivity type in a silicon substrate. In particular, the present invention relates to a method for forming twin wells in a CMOS structure.
In conventional CMOS semiconductor devices, at the well boundary there is a step height difference between N-wells and P-wells in the standard twin-well scheme which is generally around 2000 Angstroms. When a photoresist layer is applied over the well boundary between the twin wells, the step height can lead to variations in photoresist thickness in the region up to 10 micrometers wide on either side of the boundary. Due to standing wave effects which occur during photolithographic exposure of the photoresist, each variation of about 600 Angstroms, when mercury G-line exposure tools are employed, in the photoresist thickness can cause variations between the designed dimensions and the actually printed dimensions of up to 0.15 um. Until recently, this loss of dimensional control close to the well boundaries has not been of great significance since such variations accounted for less than 10% of the total designed linewidth (10% being a typical allowable design tolerance). However, linewidths are now being reduced to levels where a 0.15 um variation could account for over 15% of the total feature dimension. Such linewidth variation would effectively exclude critical circuits from within a region 10 microns wide on either side of the well boundary. Hitherto, this restriction on the critical circuit placement has not been a serious design handicap because of the well known bulk CMOS latch-up phenomenon, which itself has precluded placement of active circuitry close to the well boundaries.
However, with the availability of epitaxial silicon substrates and other developments in CMOS latch-up suppression, it has become possible to reduce the spacing between N- and P-channel sources and drains across the well boundary from around 12 microns to less than 4 microns. In order to be able fully to benefit from the advances in CMOS latch-up suppression, there is a real technical need for linewidth variations associated with the well boundaries to be reduced in order to allow the area adjacent to (i.e. within 2 to 10 microns from) the well boundaries to be fully utilized.
In addition, the presence of a step height difference at the well boundary of around 2000 Angstroms in known devices reduces the planarity of the devices. Modern VLSI devices are becoming increasingly reliant on multiple interconnect levels in order to achieve performance, functionality and reliability goals. All such schemes rely heavily on excellent planarization of the dielectric layers between the interconnect levels. Thus there is a continual technical need to increase the overall device planarity.